The present disclosure relates to a semiconductor device, and in particular, to a semiconductor integrated circuit having a layout designed by a standard cell design method.
A standard cell design has been known as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell design refers to a method of designing a large-scale integrated circuit (LSI) chip by providing in advance, as standard logic cells, unit logic elements having particular logic functions (for example, an inverter, a latch, a flip-flop, and a full adder), laying out those standard logic cells on a semiconductor substrate, and connecting those standard logic cells together with metallic interconnects.
FIG. 11 illustrates the structure of a fin transistor. Unlike a conventional complementary metal-oxide semiconductor (CMOS) transistor having two-dimensional structure, the source and drain of this fin transistor have a raised, three-dimensional structure called “fin.” The fin transistor's gate is disposed perpendicularly to this fin such that the gate wraps around a channel region defined between the source and drain in this fin. By forming the transistor with such a structure, its channel region may be controlled on three surfaces on which the gate and the fin are in contact with each other, thereby improving the channel controllability significantly compared to the conventional transistor where the channel region is controlled on a single plane only. As a result, various advantages, including reducing the leakage power, increasing the ON-state current, and lowering the operating voltage, are achieved in a semiconductor integrated circuit including such a fin transistor.
U.S. Pat. No. 8,258,577 discloses a technique for forming a standard cell using fin transistors.